ASIC Design Flow

If you aspire to work in Digital Electronics and VLSI, knowledge of Application Specific Integrated Circuits (ASICs) is vital. This course is built to take you through the stage-by-stage design of ASICs – from specification to layout generation and tapeout.

Taking this course will prepare you to work on micro-electric hardware, and equip you with essential terminologies for peer-to-peer dialogue!

What is the objective of this course?
This course is designed for engineers working in ASIC teams or aspiring to work in ASIC application, to understand the interdependencies between the various steps, the key input files used in each step, the various output files of each step, and how to assess the QoR for each step.

By the end of this you will have developed proficiency in understanding the step by step design process for Application Specific Integrated Circuits

To understand the interdependencies between the various steps
The key input files used in each step and the various output files of each step, and how to assess the QoR for each step
Distinguish yourself as an ASIC design facilitator (needs a better word as the course doesn’t make you an expert in the domain)
Create verification plans for given design specifications
Build SystemVerilog-based verification environments
Write test-cases and test-benches using SystemVerilog constructs
Perform RTL simulations using industry standard tools (I do not believe that this is applicable for this course)
Measure coverage metrics against given design specifications
Address coverage goals using knowledge of functional coverage

Introduction to ASIC Design Flow

Terminologies Associated with ASIC

Design Specification

Overview of RTL Design

RTL Verification

Logic Synthesis

Design for Testability

Logical Equivalence Check

Pre-layout Static Timing Analysis

Automatic Place and Route

Parasitic Extraction and Back-annotation

Post-layout STA

Physical Verification

DFM, Antenna Checks, and Tapeout

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E-Learning access: Three months from the time you enter a valid token number on the platform or until you complete the lab session whichever comes later. The entire program (e-Learning, Lab, and end-of-course assessment) must be completed within 6 months of purchase.

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